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Features
* Single Voltage Operation * * * * * * * * *
- 5V Read - 5V Reprogramming Fast Read Access Time - 90 ns Internal Program Control and Timer 16K bytes Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Byte-By-Byte Programming - 10 s/Byte Typical Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation - 50 mA Active Current - 100 A CMOS Standby Current Typical 10,000 Write Cycles
Description
The AT49F008 is a 5-volt-only in-system Flash Memory device. Its 8-megabits of memory is organized as 1,024,576 words by 8-bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 90 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 A. (continued)
8-Megabit (1M x 8) 5-volt Only Flash Memory AT49F008
Pin Configurations
Pin Name A0 - A19 CE OE WE RESET RDY/BUSY I/O0 - I/O7 NC Function
Addresses Chip Enable Output Enable Write Enable Reset Ready/Busy Output Data Inputs/Outputs No Connect
TSOP Top VIew Type 1
A16 A15 A14 A13 A12 A11 A9 A8 WE RESET NC RDY/BUSY A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 GND NC A19 A10 I/O7 I/O6 I/O5 I/O4 VCC VCC NC I/O3 I/O2 I/O1 I/O0 OE GND CE A0
Rev. 0972A-03/98
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To allow for simple in-system reprogrammability, the AT49F008 does not require high input voltages for programming. 5-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F008 is performed by erasing the entire 8 megabits of memory and then programming on a byte-bybyte basis. The typical byte programming time is a fast 10 s. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte pro-
gram cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
Block Diagram
DATA INPUTS/OUTPUTS I/O7 - I/O0 8 OE, CE, AND WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING FFFFFH X DECODER MAIN MEMORY (1008K BYTES) 03FFFH OPTIONAL BOOT BLOCK (16K BYTES) 00000H
VCC GND OE WE CE
Y DECODER ADDRESS INPUTS
Device Operation
READ: The AT49F008 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. ERASURE: Before a byte can be reprogrammed, the 1024K bytes memory array (or 1008K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical "1". The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical "0") on a byte-by-byte basis. Please note that a data "0" cannot be 2 programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified t BP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the AT49F008 boot block is 00000H to 03FFFH.
AT49F008
AT49F008
To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12V 0.5V. By doing this, protected boot block data can be altered through a chip erase, or byte programming. When the RESET pin is brought back to TTL levels, the boot block programming lockout feature is again active. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F008 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling, the AT49F008 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. RDY/BUSY: An open drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open drain connection allows for OR - tying of several devices to the same RDY/BUSY line. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation, puts the outputs of the device in a high impedance state, and reduces the current drawn by the part to a minimum. If the RESET pin makes a high to low transition during a program or erase operation, the operation may not be successfully completed and the operation will have to be repeated after a high level is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section). HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F008 in the following ways: (a) V CC sense: if V CC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
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Command Definition (in Hex)
Command Sequence Read Chip Erase Byte Program Boot Block Lockout Product ID Entry Product ID Exit(2)
(1)
Bus Cycles 1 6 4 6 3 3
1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 Data DOUT AA AA AA AA AA
2nd Bus Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data
6th Bus Cycle Addr Data
2AAA 2AAA 2AAA 2AAA 2AAA
55 55 55 55 55
5555 5555 5555 5555 5555
80 A0 80 90 F0
5555 Addr 5555
AA DIN AA
2AAA
55
5555
10
2AAA
55
5555
40
Product ID Exit(2) 1 XXXX F0 Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH. 2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground ............................ -0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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AT49F008
AT49F008
DC and AC Operating Range
AT49F008-90 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 5V 10% AT49F008-12 0C - 70C -40C - 85C 5V 10% AT49F008-15 0C - 70C -40C - 85C 5V 10%
Operating Modes
Mode Read Program(2) Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable RESET Product Identification VIL Hardware VIL VIH VIH A1 - A19 = VIL, A9 = VH,(3) A0 = VIL A1 - A19 = VIL, A9 = VH,(3) A0 = VIH A0 = VIL, A1 - A19 = VIL A0 = VIH, A1 - A19 = VIL Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) CE VIL VIL VIH X X X X OE VIL VIH X(1) X VIL VIH X WE VIH VIL X VIH X X X RESET VIH VIH VIH VIH VIH VIH VIL X High Z High Z Ai Ai Ai X I/O DOUT DIN High Z RDY/BUSY VOH VOL VOH VOH VOH VOH
Software(5)
Notes:
1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V 0.5V 4. Manufacturer Code: 1FH Device Code: 22H 5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol ILI ILO IPD ISB1 ISB2 ICC(1) VIL VIH VOL VOH1 VOH2 Parameter Input Load Current Output Leakage Current Power Down Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS IOL = 2.1 mA IOH = -400 A IOH = -100 A; VCC = 4.5V 2.4 4.2 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC RESET = GND 0.2V Com. CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Ind. Min Max 10 10 100 100 300 3 50 0.8 Units A A A A A mA mA V V V V V
Note:
1. ICC in the erase mode is 90 mA.
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AC Read Characteristics
AT49F008-90 Symbol tACC tCE(1) tOE(2) tDF
(3)(4)
AT49F008-12 Min Max 120 120 0 0 0 50 30
AT49F008-15 Min Max 150 150 0 0 0 70 40 Units ns ns ns ns ns 800 ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first RESET to Output Delay
Min
Max 90 90
0 0 0
40 25
tOH tRO
800
800
AC Read Waveforms
ADDRESS CE tCE tOE tACC RESET OUTPUT tRO HIGH Z OUTPUT VALID tDF tOH ADDRESS VALID
OE
Notes:
1. 2. 3. 4.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement level
3.0V AC DRIVING LEVELS 0.0V 1.5V AC MEASUREMENT LEVEL
Output Test Load
5.0V
1.8K OUTPUT PIN
tR, tF < 5 ns
1.3K
100 pF
Pin Capacitance
(f = 1 MHz, T = 25 C)
Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
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AT49F008
AT49F008
AC Byte Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 90 50 0 90 Max Units ns ns ns ns ns ns ns ns
AC Byte Load Waveforms
WE Controlled
OE tOES ADDRESS tAS CE tCS WE tWP tDS DATA IN tWPH tDH tAH tCH tOEH
CE Controlled
OE tOES ADDRESS tAS WE tCS CE tWP tDS DATA IN tWPH tDH tAH tCH tOEH
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Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 50 50 0 90 90 10 Min Typ 10 Max 50 Units s ns ns ns ns ns ns seconds
Program Cycle Waveforms
PROGRAM CYCLE OE
CE tWP WE tAS A0-A19 5555 tDS DATA AA 55 A0
INPUT DATA
tWPH
tBP
tAH 2AAA
tDH 5555 ADDRESS
Chip Erase Cycle Waveforms
OE
CE tWP WE tAS A0-A19 5555 tDS DATA AA BYTE 0 55 BYTE 1 80 BYTE 2 AA BYTE 3 55 BYTE 4 10 BYTE 5 tAH 2AAA tDH 5555 5555 2AAA 5555 tEC tWPH
Note:
OE must be high only when WE and CE are both low.
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AT49F008
AT49F008
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Parameter Data Hold Time OE Hold Time OE to Output Delay(2) 0 Min 10 10 Typ Max Units ns ns ns ns
Write Recovery Time
Notes:
1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE tOEH OE tDH I/O7 tOE HIGH Z tWR
A0-A19
An
An
An
An
An
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time
(2)
Min 10 10
Typ
Max
Units ns ns ns
150 0
ns ns
Notes:
1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE tOEH OE tDH I/O6 tOE HIGH Z tWR tOEHP
Notes:
1. 2. 3.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary.
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Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
Boot Block Lockout Feature Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 40 TO ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE(4)
OR
LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4)
PAUSE 1 second(2)
Notes:
1. 2.
Data Format: I/07 - I/O0 (Hex); Address Format: A14 - A0 (Hex). Boot block lockout feature enabled.
Notes:
1. 2.
Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). A1 - A19 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. The device does not remain in identification mode if powered down. The device returns to standard operation mode. Manufacturers Code: 1FH Device Code: 22H
3. 4. 5.
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AT49F008
AT49F008
Ordering Information
tACC (ns) 90 ICC (mA) Active 50 50 120 50 50 150 50 50 Standby 0.1 0.3 0.1 0.3 0.1 0.3 Ordering Code AT49F008-90TC AT49F008-90TI AT49F008-12TC AT49F008-12TI AT49F008-15TC AT49F008-15TI Package 40T 40T 40T 40T 40T 40T Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C)
Pakage Type 40T 40-Lead, Thin Small Outline Package (TSOP)
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Packaging Information
40T, 40-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches) *
*Controlling dimension: millimeters
(c) Copyright Atmel Corporation 1998. Atmel Corporation assumes no responsibility for the use of any circuitr y other than circuitry embodied in an Atmel Cor poration product. No other circuit patent licenses are implied. Atmel Corporation's products are not authorized for use as critical components in life suppor t devices or systems. Atmel Headquar ters, 2325 Orchard Parkway, San Jose, CA 95131, TEL (408) 441-0311, FAX (408) 487-2600 Atmel Colorado Springs, 1150 E. Cheyenne Mtn. Blvd., Colorado Springs, CO 80906, TEL (719) 576-3300, FAX (719) 540-1759 Atmel Rousset, Zone Industrielle, 13106 Rousset Cedex, France, TEL (33) 4 42 53 60 00, FAX (33) 4 42 53 60 01 Terms and product names in this document may be trademarks of others. Printed on recycled paper.
0972A-03/98/XM

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